Unix, C, Linux, Perl, System Verilog, Python, Tcl, Mixed Signal Design, EDA design flow and tools, Cadence CAD Tools

Algorithms, Perl, System Verilog, Python, Verilog RTL coding, Visio, signal processing concepts, PLDRC, HLS, CDC check, Timing Constraints, uArch, Wi-Fi standards 802.11a b g n ac ax

altium , Orcad, Verification activities, Network Analyzer, Digital Oscilloscope, ECAD tools, Prototype development, Digital Analog Mixed signal, Design Development, Zuken, Signal Generator, Boards system integration