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Lead IP Block level Verification Engineer

AMD Ventures
Hyderabad, India

Skills:

Jasper, Pcie, Verilog, System Verilog, Synopsys VC-Formal Magellan, formal property checking tools, Uvm, Cadence IEV, Synopsys VCS, HBM, Cadence IES, SVA

Early Applicant

Lead IP Block level Verification Engineer

AMD Telecom
Hyderabad, India

Skills:

Verilog, System Verilog, assertion and coverage-driven verification, Synopsys VCS, Cadence IES, formal property checking tools, Uvm, SVA

Early Applicant

Lead IP Block level Verification Engineer

Xilinx
X
Hyderabad, India

Skills:

System Verilog, Verilog, Jasper, Synopsys VCS, Synopsys VC-Formal Magellan, Uvm, Cadence IES, Simulation Tools, Cadence IEV, Formal property checking tools

Early Applicant

Lead IP Block level Verification Engineer

AMD Maquinaria
Hyderabad, India

Skills:

Verilog, System Verilog, assertion and coverage-driven verification, Synopsys VCS, Cadence IES, formal property checking tools, Uvm, SVA

Early Applicant
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