Makefile, Windows, Perl, Linux, Python, IP level ASIC verification, SystemVerilog language, UVM testbenches, automating workflows in a distributed compute environment, acceleration, formal verification, UVM concepts, simulation profile efficiency improvement, debugging RTL code using simulation tools, using AI tools, testbenches processes and flows

Makefile, Windows, Linux, Perl, Python, IP level ASIC verification, AI tools, SystemVerilog language, UVM testbenches, automating workflows in a distributed compute environment, acceleration, formal verification, UVM concepts, simulation profile efficiency improvement, debugging RTL code using simulation tools, testbenches processes and flows

Synopsys VCS, Synopsys VC Formal, HBM4, silicon debug, Cadence JasperGold, formal property checking tools, verification management tools, Uvm, systemverilog, LPDDR6

Tcl, Verilog, PERL, systemverilog, Uvm

Synopsys VCS, Synopsys VC Formal, HBM4, silicon debug, Cadence JasperGold, formal property checking tools, verification management tools, Uvm, systemverilog, LPDDR6