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Showing 3 jobs
Skills:
Perl, Shell scripting, Scan Insertion, IEEE1500, Gate-level simulation, Test cost reduction analysis, VCS simulation tool, DFT architecture, Synopsys Tetramax, Scan memory BIST, Verilog RTL design, JTAG 1149.x, ATPG pattern generation, Design for Test methodologies, Post silicon support, Mentor testkompress
Skills:
Perl, Shell scripting, DFT verification, VCS simulation tool, Synopsys Tetramax DFTMAX, IEEE1500, Scan memory BIST, JTAG 1149.x, Verilog RTL design, Mentor testkompress, Design for Test methodologies
Skills:
Perl, Shell scripting, DFT verification, VCS simulation tool, IEEE1500, Synopsys Tetramax, Scan memory BIST, Verilog RTL design, JTAG 1149.x, Design for Test methodologies, Mentor testkompress
