ASICs, formal verification, GLS low-power DV, LPDDR, Uvm, assertion-based verification, memory system architecture, systemverilog, standard IP components, performance verification

Tcp, Pcie, Ethernet, System Verilog, Forwarding logic Parsers P4, RDMA, Building test benches, Palladium, Zebu, Veloce, ASIC verification using UVM, HAPS, formal verification

Tcp, Pcie, Ethernet, System Verilog, RDMA, Data path verification performance tests, Building test benches, Palladium, Zebu, Veloce, ASIC verification using UVM, HAPS, formal verification

System Verilog, Tcp, Ethernet, Pcie, formal verification, Data path verification performance tests, Building test benches, RDMA, Zebu, HAPS, ASIC verification using UVM, Palladium, Veloce

Perl, Python, Tcl, Emulation, systemverilog, System Verilog Assertions