Jtag, C, Uart, I2c, Python, SMBus, NAND Flash products, I3C, Thermal and power management

Design for Testing (DFT), rtl development , System on a Chip (SoC) designs and integration, Verilog, Python, Perl, power analysis, LINT, processor design, cdc, arithmetic units, power closure, memory hierarchies, test plan and coverage analysis, FV, UPF checks, simulation debug, silicon bring-up, micro-architecture, bus architectures, Synthesis, ASIC SoC design verification, Timing, systemverilog, subsystem integration, accelerators, low-power design techniques

C, Perl, Linux, Bash, Python, ROS2 framework, System performance analysis, Real Time systems, x86 SoC architecture

C, Perl, Linux, Bash, Python, ROS2 framework, System performance analysis, Real Time systems, x86 SoC architecture

C, Perl, Linux, Bash, Python, ROS2 framework, System performance analysis, Real Time systems, x86 SoC architecture

C, Linux, Python, Bash, Perl, Profiling, System performance analysis, Bottleneck Analysis, Benchmarking, Embedded OSes, Performance profiling tools, Industry benchmarking suites, Hypervisors

C, Vcs, Perl, Verilog, Python, cdc, ASIC SoC development cycle, systemverilog, Rtl Design, spyglass, ASIC Design, formal verification

Embedded Software, C, C++, Networking, Network Management, Vxlan, Embedded Systems, Telecom, Broadcom Ethernet, Broadcom ASIC, Broadcom Trident, Broadcom Jericho, Broadcom Qumran, EVPN-VXLAN, L2 Networking

Pcie, timing-aware micro-architecture, high-throughput datapath, deskew, SystemVerilog RTL, design-for-test, Digital Design, UCIe, high-speed lane alignment, physical-closure collaboration, SERDES, CXL, micro-architecture

Verilog, LINT, SDC constraints, cdc, UPF, systemverilog, Rtl Design, RDC, VCLP, Synthesis, SoC integration, Makefile-based flows, Low-power design concepts, Scripting in Tcl