Minimum qualifications:

Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience.
4 years of experience in the DFT , including implementation and DFT verification for the ASIC/SoC designs.
Experience in DFT validation, including Phase-Locked Loop (PLL), sensors, Gate Level Simulations (GLS) simulation with timing, generating test cases, and debugging GLS.
Experience in IEEE1149/1500/1687, CTL generation, MBIST, HSIOs, scan, Analog IPs, and Automatic Test Pattern Generation (ATPG).
Experience with industry-standard DFT EDA tools.

Preferred qualifications:

Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science or a related field.
Experience with silicon process and technology nodes for high speed and low power consumption.
Experience in post-silicon validation and debug.
Experience in DFT and RTL

About the jobBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving team behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Responsibilities

Develop test patterns that optimally tests the logic/Memory/Analog Macro under test.
Deliver confidence in the correctness of the design for testability and debug features of the server scale CPU SoC.
Integrate DFT verification into the overall ASIC design flow.
Prepare Silicon debug verification strategy, test plan, and readiness for tester.
Participate in post manufacturing silicon bring-up tasks.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .

Silicon DFT Engineer III, Google Cloud