Tcl Scripting, Python, timing ECO generation, primetime, Fusion Compiler, ICC2, Formality, path-based debugging, LEC, Tempus, Innovus, SDC, StarRC, Parasitic Extraction, MCMM timing analysis

static timing analysis, Perl, Tcl, Makefile scripting, Synthesis, physical design CAD flow, Mentor Calibre, Power Distribution, Cadence Innovus, Cadence Genus, Floor Planning, physical design verification

Integration, Power Bi, JIRA, Confluence, Sta, Validation, Tapeout, SoC design flows, Verification, Physical Design, Dft, MS Project, ip development

foundry PDKs (28 nm and beyond), Waterfall, System Architecture, Agile, PLLs, DACs, references, floorplanning, ADCs, Comparators, clock generators, LDOs, noise budgeting, Dft, DV, Pd, Test, RTL

Agile Methodologies, JIRA, Dft, Physical Verification, Synthesis, Layout, Reliability Flow Development

automation, Synthesis, cdc, verification processes, physical design flows, MBIST, test-mode integration, methodology enhancements, Rtl Design, Dft, ATPG, silicon bring-up, production test, DFT architecture planning

Logic Design, silicon design, physical implementation, PPA trade-offs, EDA Tools, Design Methodologies, Verification, Circuit Design