Fpga, Logic Design, Verilog, Uvm, Timing Constraints, TCL scripts, regression frameworks, Timing Analysis, Power product design, System-Verilog, RTL Coding, Functional Verification, Sta, micro-architecture, ATPG generation, formal verification, synthesis scripts, Synthesis, ABV, design constraints, Digital Verification, Scan Insertion

Soc, Dft, end-to-end ASIC turnkey solutions, physical design verification, ASIC, semiconductor design, spec definition, IC services, tape-out support, RTL

Python Scripting, Tcl Scripting, primetime, Tessent DFT Compiler, PD flow awareness

FPGA Design, Silicon Validation, Analog Mixed-Signal Design, DO-254 Design Assurance, Design Verification, Functional Safety, Post-Silicon Validation, Embedded Hardware Software, Physical Design, Automotive Semiconductor Solutions, AI ML Accelerator Design, ASIC SOC design

power integrity , primetime, full-chip integration, physical verification tools, Timing Closure, Cadence Innovus, Synopsys ICC2, signoff flows

Tcl, Perl, Shell, Python, POCV, PrimeTime PX, PPA optimization, Timing ECOs, RTL Synthesis, Tempus, Crosstalk, CPF, low-power implementation, Timing Constraints, UPF, AOCV, Cadence Genus, cdc, OCV, CRPR, MCMM, clock tree architecture, Si, NXT Fusion Compiler, Timing Closure, SDC, Synopsys Design Compiler, Setup Hold Analysis

macros, Dashboards, Charts, Data Collection And Analysis, Gantt charts, ASIC development, Risk Mitigation, Program Management, resource forecasting, Graphs, Pivot Tables, Tempus Resource tool