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Showing 2 jobs
Skills:
Vcs, Gdb, Shell, Perl, Verilog, Python, ASIC design flow, floor-planning, Timing Analysis, Rtl Design, Eco, Debussy, bring-up lab debug
Skills:
Verilog, Vcs, Gdb, Timing Analysis, bring-up lab debug, ASIC design flow, Debussy, floor-planning, Eco, Rtl Design
