memory test , Scripting Languages, Static Timing Analysis, Digital Logic Design, Jtag, Hdl, BIST Architecture, Simulation, IEEE1149.1, ASIC Logic Design Flow, Gates Verification, Scan ATPG, IEEE1500, Compression Techniques, Eco

Jtag, gate-level simulations, DVT, DFT-DV, silicon debug, pattern validation, MBIST, verification plans, Scan, UPF, pattern debug, regression suites, Failure Analysis, testbenches, ATPG, pattern generation, feature validation, reset bring-up, low-power verification