System Verilog, chip design flow, Specman, performance verification of ASICs, ASIC standard interfaces, constrained-random verification environments, verification techniques, design verification methodologies, hardware verification languages, memory system architecture

Regression Analysis, Cadence Xcelium, Top-Level Verification, wreal Modeling, model validation, Cadence VIVA, Schematic-Level Correlation, Uvm, Coverage-Driven Verification, Analog Circuit Fundamentals, Waveform Debug, SV-RNM, Verification Planning, Cadence ADE Assembler, Simulation Debug, SoC AMS Verification, Digital Design Flow, Mixed-Signal SoC Integration, systemverilog, Verilog-AMS, Cadence SimVision, Cadence Virtuoso, AMS Verification Methodology, Mixed-Signal Verification

Perl, Pcie, Ethernet, Shell scripting, Python, CHI, Ace, USB 3.x, RISC-V, Uvm, Assertions, systemverilog, Axi, USB4, CXL, DDR5, DDR4, SVA

Dsp, C, Debugging, Verilog, System Verilog, Systemc, Gate-Level Simulation, Power aware verification, Uvm, Assertions, Asic Design Verification, NPU, Processor Architecture, formal verification, HVL, Digital Design, Assembly

Verilog, System Design, Automation