layout verification , Computer Engineering, System Verilog, Tcl, low-power designs, Electrical Engineering, Computer Science, Vlsi Design, design rules

layout verification , routing, Synthesis, VLSI circuits, design-for-test, sub-micron CMOS technologies, timing convergence, low-power designs, multiple power domains, RTL-to-GDS flow, Placement, timing methodology

Perl, Python, Tcl, primetime, StarRC, Cadence Innovus, Synopsys ICC2

routing, floor-planning, physical design flows, digital VLSI concepts, Tempus, Cadence Innovus, Voltus, Logic Synthesis, Rtl Design, EDA Tools, Timing Closure, Placement

power optimization , Perl, Python, Scripting, Tcl, Mentor, Timing Analysis, Cadence, Physical Design, Signal Integrity, EDA Tools, Synopsys

routing, Perl, Python, Tcl, power analysis, voltage islands, EM Analysis, power gating, physical design methodology, power rail PDN analysis, noise analysis, Logic Synthesis, current density check, Placement, power integrity concepts, Clock Tree Synthesis