C, Ovm, virtualization, Perl, Python, Tcl, Client Server centric CPU features, SystemVerilog Assertions, Validation using Emulation and FPGA HW platforms, cache controllers, x86 assembly, semi randomized test generators, Uvm, systemverilog, validation strategy development, memory coherency, debugging test failures, power management, AI based methodologies in Validation, coverage driven Validation methodologies

Test Plans, Usb, Pcie, Debugging, Ethernet, Verification Methodologies, Axi, testbenches, Uvm, systemverilog

Perl, Computer Architecture, Python, functional coverage models, debugging skills, on-chip data movement, SVA assertion-based checks, Uvm, systemverilog

python, Usb, perl, Makefile, Shell, Pcie, Ethernet, SV, Mentor, Cadence, Uvm, UCIe, MIPI, AMBA, CXL, Synopsys

Makefile, Perl, Ruby, Python, object-oriented programming, simulation debugging, power aware simulation, ASIC verification tools, Uvm, systemverilog, C-DPI, Axi, linting, AMBA, AHB

digital logic, vector processing units, Specman E, constrained-random verification, systemverilog, AI ML accelerators, Verification, IP subsystem SoCs, Debug

DDR, Usb, C, Pcie, Uart, I2c, Spi, Object-Oriented Programming, I3C, Uvm, systemverilog

code coverage , Fpga, Ovm, Test Cases, Hdl, Shell, Pcie, Verilog, Debugging, System Verilog, Python, Perl, Pci, Sta, test benches, RTL, Uvm, DDR PHY, Ethernet MAC, VHDL, ASIC, RTL top level integration, Functional coverage, Frontend Design, Logic Synthesis, HVL