C, MATLAB, Perl, Python, RF ADE, systemverilog, Parasitic Extraction, Spectre, CMOS, SERDES, Cadence Virtuoso, Mixed-Signal Verification, Verilog-A

System Verilog, Environment Development, Uvm, Design Verification, Functional Verification, Test Plan Generation

power optimization , Verilog, static timing analysis, Uvm, Synopsys, SV-based testbenches, Timing Analysis, Mentor Graphics, digital design flow, EDA Tools, coverage-driven verification, systemverilog, Rtl Design, Cadence, VHDL, Simulation

code coverage , closure , Usb, Test Plan Creation, Verilog, Assertions development, formal verification, Functional coverage, UCIe, Power-aware RTL set-up, SV, Gate-level simulations, Emulation, Fault injection, HVL, Constraint randomization, Automotive IP verification, Analog models, DPHY, UVM methodology, Mixed-mode simulations, Digital verification, Verification environment planning, Functional Verification, GLS debug skills, Simulation and debug, SERDES