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Showing 4 jobs
Skills:
Verilog, System Verilog, LPDDR, Uvm, DDR memory protocols, HBM, Functional Verification
Skills:
Verilog, System Verilog, Functional Verification, LPDDR, Uvm, DDR memory protocols, HBM
Skills:
static timing analysis, low-power design methodologies, micro-architecture development, Cadence-based ASIC design environments, SystemVerilog RTL design, Lint CDC formal verification, DFT including scan testability, Logic Synthesis
Skills:
Systemc, Test Planning, C, Shell, Tcl, Verilog, Python, systemverilog, NoC bus and interconnect verification, assertions, transaction-level modeling, UVM-based testbench development, constrained-random verification, formal verification, power-aware verification
