Minimum qualifications:

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
1 year of experience with logic design languages like Verilog, SystemVerilog or VHDL.

Preferred qualifications:

Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
1 year of experience with digital design.
Experience with logic synthesis techniques to optimize RTL code, performance and power as well as low-power design techniques.

About The Job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

In this role you will be a part of the team which designs the Tensor Processing Unit (TPU) core and sub-system. The TPU core is the heart of Google's Tensor SoC. You will be working through all phases of design and implementation. You will be working with Architects to come-up with microarchitecture specifications. You will use your logic design skills to convert the micro-arch into System Verilog code. You will be involved in Power, Performance and Area (PPA) experiments/proto-typing experiments early on to optimize PPA. You will also work closely with the verification team to verify the features implemented in design. You will also work with the Physical design (PD) team to take the design through PD cycle and eventual tape-out.

The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world.

Responsibilities

Use simulation/emulation/power analysis tools and techniques to ensure power and performance meet defined specifications.
Develop, implement, and maintain design blocks or components/part of a hardware product, and integrate design blocks or components/parts to create product subsystems.
Collaborate with cross-functional teams to debug failures (e.g., boards, software, manufacturing, design, thermal issues).

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .

ASIC Digital Design Engineer II, Silicon Engineering