python, Perl, System Verilog, test plans for DDR LPDDR IP verification, DDR-IO verification, LPDDR JDEC specifications, system verilog programming, Problem Solving Skills, coverage driven verification methodology, Uvm

Java, Agile Development Methodologies, Distributed Systems, Python, object-oriented design, open-source technologies, backend software development

PERL, Tcl, Tk, Cadence Innovus

Nosql, Frontend, Data Security, Http, Sql, Python, MTS

FPGA Design, Usb, Uart, Soc Architecture, Spi, Pcie, Verilog, Debugging, I2c, Python, Tcl, Sta, RTL Integration, cdc, UFS, memory subsystem integration, verification methodologies, DDR interfaces, EMAC, systemverilog, Multi-FPGA, FPGA Prototyping, Timing Closure

Cloud Computing, Open Source, Data Management, Debugging, Ruby, Python, Salesforce, Distribution System, CRM, Monitoring