verification methodologies, power and signaling solutions, Physical Design, PD EDA flows

Spi, Shell Scripts, Perl, Verilog, Ethernet, I2c, System Verilog, Python, Tcl, UAL, D2D PHY IP, SerDes IP, Uvm, UCIE, Asic Design Verification, formal verification, ODSP, Veloce, HAPS

verification methodologies, analog mixed signal products, power and signaling solutions, Physical Design, PD EDA flows

Unix, Automation, Asic

verification methodologies, power and signaling solutions, Physical Design, PD EDA flows

ASIC IP Design, SystemVerilog Assertions, Cadence and Synopsys front-end and middle-end design suites, systemverilog

Digital Logic Design, synchronization techniques, multi-clock domain designs, Memory Architecture, Verilog RTL coding, high-performance memory subsystems, high-speed serial interfaces, ASIC design methodologies, micro-architecture development

Perl, Pcie, Verilog, Soc, Python, Tcl, Xilinx FPGA, ONFI, Vivado Flow, LPDDR, HAPS

DDR, Perl, Verilog, Python, Tcl, spyglass, Axi, MIPI, AMBA, EDA Tools, Synopsys Design Compiler, LPDDR, AHB