Mixed-signal circuit design, PPA tradeoffs, Memory Cell Design, PLL clock-generation, Layout collaboration, Charge Pumps, Transistor-level design simulation, Clock buffers, Analog Design, Loop Filters

bandgap references , IC level issues, IC development flow, ESD LU, Silicon debugs, High speed level shifters, Design extraction and simulation flows, Temperature Sensor, Switch Cap circuits, Analog feedback loops, Analog Circuit Design, Analog Buffers, Source-Sink LDOs, Ultra-low power Oscillators, Op-Amps, Simulation and Verification, Analog layouts, LDOs, Current Sense SAR ADCs, Charge Pumps, Control Loops, Control loop architectures, Comparators

Matlab, Analog Circuit Design, Monte Carlo analysis, Architectural tradeoff analysis, AMs, Spectre, Schematic generation and simulation, Physical layout management, Signal grounding and routing tradeoffs, Block level modelling, Block level topology selection, Post layout parasitic extraction, Die area optimization, Simplis, Top level verification, Simulation verification, IC system partitioning, Cadence tool set, Worst case identification

bandgap references , temperature sensors , AC simulations, Schematic Maestro, frequency response, mixed-signal circuit design, low-noise Sigma-Delta converters, DC operating point, op-amps, mismatch analysis, biasing circuits, noise, INL, precision analog circuits, DNL, Stability, CMOS technologies, ADEXL, Layout XL, LDOs, THD, Spectre AMS, Cadence Virtuoso suite

System Engineering, Physical Design, Analog Design