hardware engineering , Deep sub-micron technology, ASIC design flows, Physical design methodologies, Circuit Design, device physics, Floorplan, Netlist2GDS

layout verification , System Verilog, Physical Design, Timing Closure, Physical verification tools, Block-level synthesis, power analysis, Floor-planning, Vlsi Design, Design rules, Place-and-route

layout verification , routing, Synthesis, VLSI circuits, design-for-test, sub-micron CMOS technologies, timing convergence, low-power designs, multiple power domains, RTL-to-GDS flow, Placement, timing methodology

power optimization , Perl, Python, Scripting, Tcl, Mentor, Timing Analysis, Cadence, Physical Design, Signal Integrity, EDA Tools, Synopsys

routing, Perl, Python, Tcl, power analysis, voltage islands, EM Analysis, power gating, physical design methodology, power rail PDN analysis, noise analysis, Logic Synthesis, current density check, Placement, power integrity concepts, Clock Tree Synthesis

PnR-Floorplan Macro placement, EM IR understanding and fixes, STA analysis, Util area reduction experiments, ECO cycle, Density Congestion Timing issues and fixes on lower tech nodes 5nm, Physical aware Synthesis using FC, PV closure