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Showing 4 jobs
Skills:
Perl, Ruby, System Verilog, make, Uvm
Skills:
Perl, Ruby, System Verilog, make, Uvm
Skills:
Perl, Python, constraint-random tests, Power-aware verification, formal static verification techniques, coverage-driven verification methodologies, Uvm, systemverilog
Skills:
Vcs, JIRA, Git, Bitbucket, Perl, Verilog, Python, Tcl, CVS, Gate-Level Simulation, Xcelium, Palladium, Uvm, systemverilog, Assertions, Zebu, Protium, Questa, RTL-to-Gate-Level Simulation, HAPS, SoC Verification
