Perl, Pcie, Python, Verdi, Cadence Xcelium Simulator, CHI, Ace, JasperGold, GPUs, ARM CPU, AMBA protocols, Uvm, Synopsys VCS, ATB, Axi, HBM, Network on chip, VC Formal, LPDDR, DLA

Makefile, Perl, Ruby, Python, object-oriented programming, simulation debugging, power aware simulation, ASIC verification tools, Uvm, systemverilog, C-DPI, Axi, linting, AMBA, AHB

Perl, Python, constraint-random tests, Power-aware verification, formal static verification techniques, coverage-driven verification methodologies, Uvm, systemverilog

Verilog, VMM, assertion-based verification, Uvm, functional coverage, advanced verification methodologies, systemverilog

Perl, Makefile, Ruby, Python, C-DPI, Axi, AMBA, ASIC verification tools, Uvm, AHB, systemverilog

firmware interaction, AMs, Mentor, Cadence, Uvm, systemverilog, Register models, industry VIPs, Calibration and link training flows, Avery, SERDES, Siemens, Synopsys

Calibration, Synopsys, firmware interaction, Uvm, AMs, systemverilog, Mentor, Cadence, link training, Siemens, Register models, industry VIPs, Avery, SERDES