Fpga, Perl, Python, object-oriented programming, RTL, emulation platforms, test plan development, Uvm, automation scripts, systemverilog

Perl, Verilog, Python, Tcl, VHDL, Uvm, systemverilog

Makefile, Perl, Ruby, Python, object-oriented programming, simulation debugging, power aware simulation, ASIC verification tools, Uvm, systemverilog, C-DPI, Axi, linting, AMBA, AHB

bandwidth management , Microprocessor Cores, hierarchical memory subsystems, Specman E, Debug, IP subsystem SoCs, packet processing, Verification, congestion control, systemverilog, constrained-random verification

Computer Architecture, Debugging, Uvm, systemverilog, Coverage-Driven Verification, Constrained-Random Testing, formal verification, Functional Verification, Testbench Development, Verification Planning, Formal Tools, Rtl Design

Perl, Pcie, Ethernet, Shell scripting, Python, CHI, Ace, USB 3.x, RISC-V, Uvm, Assertions, systemverilog, Axi, USB4, CXL, DDR5, DDR4, SVA