C, Vcs, Verilog, Perl, EVE, spyglass, formal verification, Timing-analysis, Flow automation, Hardware Emulation Platforms, systemverilog, ASIC Design, cdc, Rtl Design, ASIC SoC development cycle, Specification design, Power-optimization, Veloce

C, Vcs, Verilog, Perl, Timing-analysis, formal verification, spyglass, Flow automation, Hardware Emulation Platforms, systemverilog, ASIC Design, cdc, Rtl Design, ASIC SoC development cycle, Specification design, EVE, Power-optimization, Veloce

C, Vcs, Perl, Verilog, cdc, Hardware Emulation Platforms, Specification design, power-optimization, ASIC SoC development cycle, systemverilog, Rtl Design, flow automation, spyglass, timing-analysis, EVE, Veloce, ASIC Design, formal verification

C, Bash, Perl, Linux, Python, Profiling, ROS2 framework, Embedded OSes, System performance analysis, Robotics algorithms, Post-silicon validation, Bottleneck Analysis, Performance profiling tools, Industry benchmarking suites, Hypervisors

C, Python, Bash, Perl, Linux, Embedded OSes, System performance analysis, Hypervisors, Profiling Tools, Benchmarking suites

VLAN, C Programming, Iptables, Vxlan, Qos, Linux kernel-based networking subsystems, Linux firewall mechanisms, Wi-Fi, Bridges, Networking feature development, Linux-based platforms, Gre, Linux kernel networking architecture, Data path control plane features, nftables, Drivers and modules for networking hardware, Offload acceleration