layout verification , Computer Engineering, System Verilog, Tcl, low-power designs, Electrical Engineering, Computer Science, Vlsi Design, design rules

routing, Perl, Python, Tcl, power analysis, voltage islands, EM Analysis, power gating, physical design methodology, power rail PDN analysis, noise analysis, Logic Synthesis, current density check, Placement, power integrity concepts, Clock Tree Synthesis

PnR-Floorplan Macro placement, EM IR understanding and fixes, STA analysis, Util area reduction experiments, ECO cycle, Density Congestion Timing issues and fixes on lower tech nodes 5nm, Physical aware Synthesis using FC, PV closure

clock distribution , Clp, PERL, Tcl, low power design, Sta, PERC, Signal Integrity Analysis, LVS, LEC flow, Tape Out, IP integration, Dfm, Timing Closure, Physical Verification, Synthesis, Gds, Tk, cpf, Clock Tree Synthesis, upf, PNR, Physical Design, ERC, DRC, Floorplan

hardware engineering , Perl Scripting, Sta, Circuit Level Comprehension, Low Power Flow, RTL to GDSII Implementation, Leakage Power, Signal Integrity, Multi-Vt Flow, IC design, Verification, Dfm, Power Supply Management, Deep Sub-Micron Design, Physical Design, Constraints Validation, High Frequency Design, Power Gating, PDN Methodology, PPA Targets, Timing Signoff