cache coherency , Scripting, Noc, DDR, C Programming, Performance Verification, RTL environments, SystemC TLM simulation, TLV CI flow, UVM VIPs, Performance simulation tools, systemverilog, Coresight, Formal connectivity verification, Memory hierarchy, VHDL, RTL debugging, Gate level simulation, Interconnect architectures, ASIC Top level verification, Hardware emulation

C, Bash, Perl, Verilog, System Verilog, Python, Systemc, CPU architecture, approximate models, graphics pipeline, memory subsystem architecture, Emulators, TLM, performance simulators