boundary scan , Vcs, System Verilog, primetime, Memory BIST, Logic Equivalency checking, Scan and BIST architectures, TetraMax, Gate level simulation debugging, JTAG protocols, ATPG, EDA Tools, Tessent tool sets, TestMax

Networking Protocols, spyglass, Verilog RTL coding, Verplex LEC, high-speed serial interfaces, Synopsys Design Compiler, ASIC Design, multi-domain clock synchronization, high performance memory subsystems, ASIC debugging

Vcs, System Verilog, primetime, Logic Equivalency checking, TetraMax, JTAG protocols, Tessent, Gate level simulation, ATPG, EDA Tools, BIST architectures, TestMax

DDR, Perl, Verilog, Python, Tcl, spyglass, Axi, MIPI, AMBA, EDA Tools, Synopsys Design Compiler, LPDDR, AHB

Perl, Pcie, Verilog, Soc, Python, Tcl, Xilinx FPGA, ONFI, Vivado Flow, LPDDR, HAPS

Jasper, Verilog, System Verilog, Cadence IEV, Synopsys VCS, Synopsys VC-Formal Magellan, Cadence IES, Formal property checking tools, Uvm, Simulation Tools

code coverage , Fpga, Ovm, Test Cases, Hdl, Shell, Pcie, Verilog, Debugging, System Verilog, Python, Perl, Pci, Sta, test benches, RTL, Uvm, DDR PHY, Ethernet MAC, VHDL, ASIC, RTL top level integration, Functional coverage, Frontend Design, Logic Synthesis, HVL