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ASIC DFT Engineer/ ASIC Engineer

Cisco Home
Bengaluru, India

Skills:

Vcs, System Verilog, primetime, Logic Equivalency checking, TetraMax, JTAG protocols, Tessent, Gate level simulation, ATPG, EDA Tools, BIST architectures, TestMax

Early Applicant

Senior RTL Design Engineer (ASIC)

ALTEN Calsoft Labs
Bengaluru, India

Skills:

DDR, Perl, Verilog, Python, Tcl, spyglass, Axi, MIPI, AMBA, EDA Tools, Synopsys Design Compiler, LPDDR, AHB

Early Applicant

ASIC DFT Engineer || DFT/ATPG/MBIST/SCAN/JTAG || 8+ years

Cisco Live
Bengaluru, India

Skills:

Vcs, ATE patterns, Scan Insertion, Tessent, JTAG protocols, ATPG, Gate level simulation, Post-silicon validation, P1687, TestMax, TetraMax

Early Applicant

Senior ASIC/FPGA Design & Verification Engineer

atria logic inc.
Bengaluru, India

Skills:

code coverage , Fpga, Ovm, Test Cases, Hdl, Shell, Pcie, Verilog, Debugging, System Verilog, Python, Perl, Pci, Sta, test benches, RTL, Uvm, DDR PHY, Ethernet MAC, VHDL, ASIC, RTL top level integration, Functional coverage, Frontend Design, Logic Synthesis, HVL

Early Applicant

ASIC DFT Engineer || DFT/ATPG/MBIST/SCAN/JTAG || 8+ years

Sell Cisco
Bengaluru, India

Skills:

Vcs, Perl, Python, Tcl, Scan Insertion, Post-silicon validation, P1687, TetraMax, Gate level simulation debugging, ATE patterns, JTAG protocols, ATPG, Tessent tool sets, TestMax

Early Applicant

Lead ASIC RTL Design Engineer

leadsoc technologies pvt ltd
Bengaluru, India

Skills:

Perl, Verilog, Python, Tcl, microarchitecture development, Synthesis, cdc, systemverilog, Rtl Design, RDC, EDA Tools, LINT, low-power methodologies, STA concepts

Early Applicant
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