Static Timing Analysis, Tcl, Python, Perl, Scripting Languages, routing, Cadence Genus, physical design constraints, physical design flow, Cadence Innovus, debug skills, EDA Tools, Cadence Cerebrus, IC design, clock placement, Power, Timing

Eda, Machine Learning, Artificial Intelligence, automation, physical implementation, extraction and simulation workflows, generative AI, design migration and design reuse, analog and custom IC design, LVS, OpenAccess-based design environments, semiconductor design, Physical Verification, circuit simulation SPICE, DRC, Parasitic Extraction, analog verification flows, standard cell design and optimization, Cadence Virtuoso