Cadence tool experience, jitter and signal equalization techniques, Phase Interpolator, layout and physical verification, CMOS design, High Speed Clock Distribution, Bias and Bandgap Voltage Regulators, Low jitter PLL, CAD tools for circuit simulation, SERDES

layout and physical verification, Cadence tool experience, jitter and signal equalization techniques, Phase Interpolator, CMOS design, High Speed Clock Distribution, Bias and Bandgap Voltage Regulators, Low jitter PLL, CAD tools for circuit simulation, SERDES

static timing analysis, Python, Verilog RTL, Genus Design Compiler, scripting or programming languages, DFT methodologies, high-speed SerDes, ASIC synthesis, Asic Physical Design, physical verification DRC LVS, 3DIC implementation methodologies, Cadence Virtuoso, RTL Compiler, place-and-route Encounter Innovus ICC, Clock Tree Synthesis

synopsys tools , Verilog RTL coding, Power Compiler, formal verification tools, IC Compiler, primetime, Design Compiler, CMOS VLSI development, Digital Design