About SiFive

As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive's unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.

At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.

Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time.

Are you ready

To learn more about SiFive's phenomenal success and to see why we have won the GSA's prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.

Job Description:

Role Overview

We are looking for a seasoned Senior / Lead Design Verification (DV) Engineer with 8+ years of experience to champion correctness of our next-generation, high-performance silicon. This is a unique role designed for a DV expert who can fluidly bridge the gap between mathematical rigor (Formal Verification) and scalable, dynamic environments (UVM Simulation).

You will own the verification strategy for highly complex, high-risk blocks and subsystems (such as complex control logic, arbiters, caches, and high-speed fabrics). Your mission will be to deploy the optimal mix of simulation and formal techniques to eliminate deep-cycle architectural bugs and drive the design to 100% sign-off.

Key Responsibilities

Dual-Pronged Verification Strategy: Analyze architectural specifications to author comprehensive testplans that explicitly partition features into Formal Verification (FV) targets or Constrained-Random Simulation targets based on efficiency and risk.
Formal Environment Architecture: Architect and deploy block-level and end-to-end formal verification environments. Write robust SystemVerilog Assertions (SVA), define assumptions, develop helper models, and apply complexity-reduction techniques to achieve full mathematical proofs.
UVM Simulation Ownership: Build, maintain, and scale robust, constrained-random simulation environments using SystemVerilog (SV) and UVM. Develop scalable sequences, monitors, and scoreboards.
Deep-Cycle Bug Hunting: Root-cause highly complex, concurrent, and structural RTL bugs that are difficult or impossible to hit with traditional simulation alone.
Hybrid Sign-Off Metrics: Achieve complete coverage closure by effectively mapping and merging simulation metrics (code/functional coverage) with formal metrics (proof completeness, bounded proofs, and formal core analysis).
Collaboration : Work closely with RTL designers and architects to resolve ambiguities in specifications.

Experience

Required Skills & Qualifications

8+ years of dedicated experience in ASIC/SoC Design Verification with a track record of successful tape-outs.

Education:

Bachelor's or Master's in ECE/EEE/VLSI/Embedded Systems

Technical Competencies

Formal Verification Mastery: Expert-level knowledge of property checking, model checking, and sequential equivalence. Deep fluency in SVA (SystemVerilog Assertions) and writing formal-friendly constraints.
Simulation & UVM Expertise: Mastery of SystemVerilog (SV), OOP design patterns, and advanced UVM architectures.
Industry Tool Proficiency: * Formal Tools: Cadence JasperGold, Synopsys VC Formal, or Siemens OneSpin.
Simulation/Debug Tools: Synopsys VCS, Cadence Xcelium, and Verdi.
Complexity Management: Proven ability to resolve formal state-space explosion utilizing abstractions, induction, black-boxing, and cut-points.
Domain Knowledge: Strong understanding of digital design fundamentals, clock domain crossing (CDC), reset domain crossing (RDC), and complex logic (e.g., multi-layered arbiters, credit-based flow control, pipelines, or coherent caches).
Protocols: Hands-on experience verifying standard protocols like AXI, CHI, PCIe, CXL, or similar high-performance bus fabrics.
Automation: Strong scripting skills (Python, Perl, or Tcl) to automate verification regressions and parse multi-tool results.

Soft Skills

A critical, analytical break-the-design mindset combined with methodical problem-solving skills.
Excellent communication and documentation skills, with the ability to clearly present formal verification strategies and sign-off bounds to non-formal stakeholders.
Proven ability to drive tasks independently and lead technical initiatives.

Additional Information:

This position requires a successful background and reference checks and satisfactory proof of your right to work in:

India

Any offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.

SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.

Senior / Lead Design Verification Engineer (Formal & Simulation)