Vcs, Perl, Python, Tcl, Xcelium, AMBA-based interconnect fabrics, AXI-Lite, Uvm, systemverilog, Axi, APB, AI-assisted engineering tools, Questa, AHB

Machine Learning, Data Analytics, Python, Deep Learning, Document-processing pipelines, LLM-based workflows

Digital Logic Design, Scripting, LINT, cdc, formal equivalence, DSP fundamentals, ECO flows, Processor SoC architecture, micro-architecture, SoC Designs

Tcl, System Verilog, Python, Perl, Vcs, Questa, Uvm, Modelsim

PowerShell, Python, SOTI MobiControl, HP Thin Clients, Enterprise MDM

Static timing analysis, ASIC development flow, Constraints generation, SOC design, Sta, Timing Closure