Verplex LEC, spyglass, Verilog RTL coding, high-speed serial interfaces, Synopsys Design Compiler, multi-domain clock synchronization, high performance memory subsystems, ASIC debugging

rtl development , Physical Design, Digital Design, Micro-architecture, Verification

Digital RTL Design, VHDL, Timing Analysis, Low-Power Design Techniques, Logic Synthesis, systemverilog

Networking Protocols, Ethernet, Fcoe, multi-domain clock synchronization, spyglass, high-speed serial interfaces, high performance memory subsystems, Verplex LEC, ASIC debugging, ASIC Design, Synopsys Design Compiler, Verilog RTL coding

Vcs, Gdb, micro architecture definition, RTL coding using Verilog, scripting knowledge, Simulation Tools, Synthesis, interconnect design, LINT, debug tools like Debussy, design and verification tools, cache controller design

Verilog, Cache, Soc Architecture, fabric coherence, memory compression, systemverilog, logic synthesis techniques, FPGA and emulation platforms, digital logic design principles, Synthesis, DRAM, FPGA design verification, assertion-based formal verification, RTL design concepts, Dft, low-power design techniques, power analysis

static timing analysis, Python, Verilog RTL, Genus Design Compiler, scripting or programming languages, DFT methodologies, high-speed SerDes, ASIC synthesis, Asic Physical Design, physical verification DRC LVS, Cadence Virtuoso, 3DIC implementation methodologies, RTL Compiler, place-and-route Encounter Innovus ICC, Clock Tree Synthesis