Mentor Graphic Calibre DRC, Physical verification of custom layout, Analog Layout fundamentals, Cadence VLE

boundary scan , ATPG (Automatic Test Pattern Generation), LBIST (Logic Built-In Self-Test), DFT DRC (Design Rule Checking), Jtag, Perl, Python, Tcl, LINT, ASIC design flow, cdc, Scan compression, Scan stitching, Low power DFT Techniques, RTL Coding, ATPG Coverage improvement, DFT STA Constraint development, Analog Phy DFT

Physical Verification, DRC, LVS, ERC, PERC, Dfm