SV UVM, C models for DSP, Ethernet IEEE 802.3, Gate level simulations, DisplayPort, MIPI protocols, Formal Gate level Power aware Verification, ARM based SoC verification, ASIC verification concepts

rtl development , Noc, Soc Architecture, Verilog, Logic Design, PPA, interconnects, Complex SoC, Uvm, systemverilog, Rtl Design, Logic Synthesis, Memory Architecture, Dft, DV, Arteris, power management, CPU Architecture, RTL Coding, micro-architecture, Hardware Architecture, Digital Design