Tcl Scripting, Perl, Python, Innovus, primetime, ICC2, Parasitic estimation, Semi-automated floorplanning

routing, Physical Design, Place And Route, PNR, floorplanning, CTS

Cadence - Virtuoso, Perl, Python, Tcl, Mentor tools, SV, Verilog Hdl, Cadence, Uvm, Spice Simulator, Verilog-AMS, AMS simulation environment, Verilog-D, Synopsys, Verilog-A

Ovm, Database Management, Verilog, System Verilog, silicon debug, verification management tools, formal property checking tools, Uvm, memory controller protocols, assertion and metric-driven verification, Synopsys VCS, gate level simulation, power verification, reset verification, Cadence IES, contention checking, calibration board skew and jitter modeling

MATLAB, Cadence Design Environment, IBIS and IBIS-AMI, Signal Integrity Design, Electrical Package Design Techniques, Electromagnetic and Transmission Line Theory, Pcb Layout

Ovm, Database Management, Verilog, System Verilog, high speed interface verification, silicon debug, verification management tools, formal property checking tools, Uvm, Synopsys VCS, gate level simulation, power verification, Cadence IES, reset verification, contention checking, metric-driven verification