Digital Logic Design, synchronization techniques, multi-clock domain designs, Memory Architecture, Verilog RTL coding, high-performance memory subsystems, high-speed serial interfaces, ASIC design methodologies, micro-architecture development

C, Vcs, Perl, Verilog, cdc, Hardware Emulation Platforms, ASIC SoC development cycle, systemverilog, Rtl Design, spyglass, EVE, Veloce, ASIC Design, formal verification

Networking Protocols, Ethernet, Fcoe, multi-domain clock synchronization, spyglass, high-speed serial interfaces, high performance memory subsystems, Verplex LEC, ASIC debugging, ASIC Design, Synopsys Design Compiler, Verilog RTL coding

C, Vcs, Perl, Verilog, cdc, Hardware Emulation Platforms, ASIC SoC development cycle, systemverilog, Rtl Design, spyglass, EVE, Veloce, ASIC Design, formal verification

C, Vcs, Perl, Verilog, cdc, Hardware Emulation Platforms, ASIC SoC development, systemverilog, Rtl Design, spyglass, EVE, ASIC Design, Veloce, formal verification

Vcs, Gdb, micro architecture definition, RTL coding using Verilog, scripting knowledge, Simulation Tools, Synthesis, interconnect design, LINT, debug tools like Debussy, design and verification tools, cache controller design

DDR, Perl, Verilog, Python, Tcl, spyglass, Axi, MIPI, AMBA, EDA Tools, Synopsys Design Compiler, LPDDR, AHB

code coverage , Fpga, Ovm, Test Cases, Hdl, Shell, Pcie, Verilog, Debugging, System Verilog, Python, Perl, Pci, Sta, test benches, RTL, Uvm, DDR PHY, Ethernet MAC, VHDL, ASIC, RTL top level integration, Functional coverage, Frontend Design, Logic Synthesis, HVL