Physical Verification, foundry rule decks, Antenna Verification, ERC, Metal Fill Verification, DRC, PV signoff methodologies, LVS, Density Verification, advanced process technologies, PV automation scripts

HDL - Verilog, Logic Design, Tcl, shell scripting, System Verilog, Perl, Synthesis, EDA Tools, Genus Synthesis Solution, low power design, Cadence Tools, Physical Design, formal verification, Timing Closure

HDL - Verilog, Logic Design, shell scripting, Tcl, System Verilog, EDA Tools, Synthesis, Genus Synthesis Solution, low power design, Cadence Tools, Physical Design, Automation skills using Perl, formal verification, Timing Closure