Job Requirements

At Quest Global, it's not just what we do but how and why we do it that makes us different. With over 25 years as an engineering services provider, we believe in the power of doing things differently to make the impossible possible. Our people are driven by the desire to make the world a better place—to make a positive difference that contributes to a brighter future. We bring together technologies and industries, alongside the contributions of diverse individuals who are empowered by an intentional workplace culture, to solve problems better and faster.

Key Responsibilities

Expertise in Low Power Synthesis with MCMM Aware and Logical/Physical Aware Synthesis
Strong knowledge and expertise in Low Power Designs, UPF/CPF Terminologies and Fundamentals
Experience with advanced low power design techniques.
Experience with advanced technology nodes like 2nm, 3nm, 4nm.
Collaborate with RTL and verification teams to ensure design requirements and power goals are met from synthesis through final signoff.
Ensure proper power intent using UPF/CPF, ensuring low power design techniques (e.g., power gating, clock gating, voltage scaling) are implemented across the flow.
Proven experience in physical design, with in-depth knowledge of synthesis, floorplan, placement, clock tree synthesis, routing, and signoff (Static Timing Analysis, Formal Verification, Power Signoff, Physical Verification)
Knowledge of high-performance digital designs and custom ASIC flows.
Strong problem-solving skills and ability to analyze complex design challenges.
Excellent communication skills and ability to collaborate in a fast-paced, cross-functional team environment.

We are known for our extraordinary people who make the impossible possible every day. Questians are driven by hunger, humility, and aspiration. We believe that our company culture is the key to our ability to make a true difference in every industry we reach. Our teams regularly invest time and dedicated effort into internal culture work, ensuring that all voices are heard.

We wholeheartedly believe in the diversity of thought that comes with fostering a culture rooted in respect, where everyone belongs, is valued, and feels inspired to share their ideas. We know embracing our unique differences makes us better, and that solving the worlds hardest engineering problems requires diverse ideas, perspectives, and backgrounds. We shine the brightest when we tap into the many dimensions that thrive across over 21,000 difference-makers in our workplace.

Work Experience

Expertise in Low Power Synthesis with MCMM Aware and Logical/Physical Aware Synthesis
Strong knowledge and expertise in Low Power Designs, UPF/CPF Terminologies and Fundamentals
Experience with advanced low power design techniques.
Experience with advanced technology nodes like 2nm, 3nm, 4nm.
Collaborate with RTL and verification teams to ensure design requirements and power goals are met from synthesis through final signoff.
Ensure proper power intent using UPF/CPF, ensuring low power design techniques (e.g., power gating, clock gating, voltage scaling) are implemented across the flow.
Proven experience in physical design, with in-depth knowledge of synthesis, floorplan, placement, clock tree synthesis, routing, and signoff (Static Timing Analysis, Formal Verification, Power Signoff, Physical Verification)
Knowledge of high-performance digital designs and custom ASIC flows.
Strong problem-solving skills and ability to analyze complex design challenges.
Excellent communication skills and ability to collaborate in a fast-paced, cross-functional team environment.

Lead Engineer PD