power integrity , Perl, Python, Tcl, Sta, primetime, Cadence Innovus, Tempus, EM IR analysis, Voltus

power integrity , Timing Closure, Process node design rules, Physical Design methodologies, Cadence toolchain, Signal Integrity

routing, floorplanning, Signal Integrity, CTS, Timing Closure, Placement, IR EM and variability analysis, low-power design, ASIC SOC physical design implementation, Physical Verification