Tcl, Python, Shell, Soc Architecture, Rtl Design, UVM verification flows, Linux environments, Siemens Veloce, Synopsys ZeBu, systemverilog

Jtag, Pcie, Uart, Ocp, Axi, Zebu, FPGA emulation, C-SV UVM

clocking , Verilog, System Verilog, SOC Emulation, SOC boot flow, Power management flows, Synthesis, PNR, FPGA based prototyping platforms, Low Power Verification, System Verilog Assertions, RTL GLS level simulations, Platform bring up in Emulators or Silicon, Emulation platforms, Functional Verification, Timing Analysis

lattice , System Verilog, Usb, Verilog, Ethernet, Ddr3, C, Pcie, ARM Cortex platforms, SystemC-DPI testing methodologies, embedded processors, processor architectures, FPGA architectures, SERDES, AHB, Xilinx, VirtuaLAB environments, Altera, APB, RTL synthesis concepts, DSP theory, Veloce platforms, UVM-acceleration, AMBA, Microsemi