UVM (Universal Verification Methodology), SVA (SystemVerilog Assertions), C, C++, Shell, Pcie, Perl, Arm, Python, Tcl, Systemc, MCU, Hardware Emulation Platforms, RISC-V, UCIe, systemverilog, Verification Methodology, AMBA, Axi, Formal Model Equivalence Checking Tools, formal verification, VC Formal

Device Drivers, C, shell scripting, Python, security features, WiFi performance tuning, rate control algorithms, Linux WiFi stack, 802.11 standards, embedded platforms, Linux operating systems, hostapd, system-level concepts, computer networking fundamentals, Wi-Fi experience, power management, MAC layer PHY interaction

Perl, Python, Tcl, RISC-V architecture, systemverilog

Arm, formal verification, RTL, Digital Design, Uvm, systemverilog, RISC

Coverage, complex debug, CPU DV, RTL, regressions, high-performance out-of-order CPU verification, microarchitecture verification, testbench development, Uvm, AI-assisted verification workflows, Isa, CVM, verification strategy

Pcie, System Verilog, Python, Systemc, Hybrid test benches, MDV, DV signoffs, SV, Uvm, UCIe, Axi, CDV

Perl, Python, Tcl, Xcelium simulation, vManager, Real-Number Modeling, Verilog-AMS, JasperGold, Uvm, SVA, systemverilog

computational design , wiring diagrams , High Voltage (HV) transmission and distribution substations, Secondary systems electrical design, P&C schematics, Automation of data manipulation, P&C room layout, CAD documentation to UK Energy standards, Protection coordination, ETAP software, Design algorithms

Clarity, MIPI D-PHY, Cadence Sigrity, PCIe Gen5, TDR, 10 Gigabit Ethernet, USB 3.x, VNA, SIwave, Keysight ADS, MIPI CSI, Ansys HFSS, high-bandwidth oscilloscopes, C-PHY, LPDDR memory channels