Shell, Pcie, Perl, Arm, Python, Tcl, MCU, AMBA, Axi, UCIe, systemverilog

System Verilog, formal verification methodologies, C testcases, scripting for flow integration, Uvm, AI ML-driven EDA tools

Vcs, Pcie, Python, Perl, Ethernet, Tcl, Xcelium, Uvm, Testbench Architecture, LPDDR4, Functional Coverage, Verdi, UCIe, systemverilog, Axi, MIPI, Constrained Random Verification, APB, DVE, USB4, USB3, Questa, CXL, DDR5, DDR4, AHB, SVA

synopsys primetime , Perl, Python, Tweaker, Power-Aware Verification UPF, Cadence CCD, Sign-off STA Synopsys PrimeTime PT PT-PX, Cadence Conformal LEC, PrimeClosure, Cadence Tempus, Synopsys Formality, Formal Verification LEC, Constraints Validation Synopsys TCM GCA Ausdia TimeVision SpyGlass, Timing Closure ECO Cadence Tempus

Hmc, Arm, Ethernet, Pcie, DDR, Functional Safety verification, formal verification, Assertions, UCIe, Uvm, Security verification, systemverilog, Emulation, coverage-driven verification, SoC Verification, AI-assisted verification, RISC-V, Portable Stimulus PSS, Zebu, HBM, Palladium, Hardware software co-verification, Veloce

Typescript, Javascript, Automation Frameworks, Python, AI orchestration frameworks, AWS cloud services, cloud-native applications, AI agents

Perl, Python, verification methodologies, low power verification, system level performance analysis, Uvm, systemverilog, RTL development environments, test bench infrastructure, emulation platforms, test plan development, automation scripts

Ml, Java, C, Microservices, Kubernetes, Python, cloud-native systems, LLMs, Go, Ai, Tetragon, eBPF, Zero Trust

register modeling, protocol VIP integration, Uvm, systemverilog

Test Case Creation, Shell, Perl, Python, Advanced Debugging skills, Uvm, testbench development, coverage-driven verification, Computer Architecture concepts, Formal Verification techniques, Functional Verification, Rtl Design