control logic , Verilog, Rtl Design, Synthesis, systemverilog, Error handling, cdc, Sta, Ethernet standards, Digital micro-architecture, PCS functionality, Link monitoring, state machines, Packet processing, RDC, Safety mechanisms

power optimization , Static Timing Analysis, Design-for-Debug, SoC Debug architectures, low power design techniques, constraints development for Physical Design implementation, SoC integration, Design-for-Test, power analysis

static timing analysis, Verilog, Python, Tcl, SDC development, Tempus, Cadence Innovus, simulation methodologies, Rtl Design, transistor-level concepts, Genus, digital circuit operation, custom layout fundamentals, place-and-route, multi-clock designs, Synthesis, digital design fundamentals, floorplanning, Physical Verification, systemverilog, CDC concepts, Timing Constraints, Liberty timing models, characterization concepts

Fpga, Microprocessors, Embedded Firmware, definition of electrical schematics, product design board level testing, manufacturing failures analysis, component obsolescence treatment, electronic design and development, alternative solution identification, integration and validation testing, test procedures definition and execution, product performance evaluation, Dfmea, hardware design development and testing, high-speed digital and analog electronic circuits, troubleshooting skills on Electrical Electronic boards, DFM tools, Hardware Verification, boards place route including signal integrity, Dft, Microcontrollers, Design and simulation tools

Vcs, Tcl, Verilog, System Verilog, Python, Perl, Sec, Questa, spyglass, LINT, Xcelium, cdc, Jasper-FPV, Questa CDC, RDC

boundary scan , Tcl, Python, Perl, Scripting Languages, test pattern generation, silicon bring-up, scan compression, JTAG IEEE 1149.1, ATPG, DFT EDA tools, post-silicon debug, DFT methodologies, Cadence Modus Genus, memory BIST, Scan Insertion