Verilog, System Verilog, Digital Logic Design, Synthesis, Pre-Silicon Verification, Post-Silicon Support

UNIX, Debugging, Verilog, ASIC SoC design methodologies, systemverilog, design quality checks, RTL Coding, RTL integration, Windows environments, Ms Office Tools, Digital Design, Simulation, SoC connectivity concepts

static timing analysis, Synthesis, multi-power-domain design techniques, Simulation, Uvm, FPGA design methodologies, formal verification tools such as Siemens Questa Formal and Synopsys Spyglass

Firmware Development, FPGA Design, Verilog, Static Timing, ASIC design flow, Synthesis, datapath timing analysis, digital design principles, high-speed data transmission, systemverilog, CMOS digital circuits, Rtl Design, Dft, front-end tools, mixed signal concepts, Verification, clock design

boundary scan , Perl, Scripting Languages, Python, Tcl, scan compression, JTAG IEEE 1149.1, Scan Insertion, memory BIST, DFT methodologies, DFT EDA tools, test pattern generation, ATPG, silicon bring-up, post-silicon debug, Cadence Modus Genus

Pcie, Version Control, Ethernet, RTL synthesis, Documentation, Timing Closure, verification processes, silicon bring-up, bare metal firmware development, SERDES, AI tools like Cursor

Vcs, Perl, Verilog, System Verilog, Python, Tcl, LINT, cdc, Xcelium, spyglass, RDC, Questa, Questa CDC