Usb, C, Makefile, Windows, Shell, Pcie, Linux, Perl, Verilog, Ethernet, Ruby, System Verilog, Systemc, IP level ASIC verification, acceleration HLS tools, Graphics pipeline knowledge, UVM testbenches, automating workflows in a distributed compute environment, AXI ACE Protocols, simulation profile efficiency improvement, UVM based verification frameworks, TLM, debugging firmware and RTL code using simulation tools

Perl, Python, Tcl, Assertions SVA, Constrained-random verification, Uvm, Functional coverage, systemverilog

Jasper, Pcie, Verilog, System Verilog, Synopsys VC-Formal Magellan, formal property checking tools, Uvm, Cadence IEV, Synopsys VCS, Cadence IES, HBM, DDR4, AXI3, SVA

C, Makefile, Windows, Shell, Perl, Linux, Verilog, Ruby, System Verilog, Systemc, IP level ASIC verification, graphics pipeline knowledge, HLS tools, UVM testbenches, automating workflows in a distributed compute environment, developing UVM based verification frameworks, simulation profile efficiency improvement, TLM, debugging firmware and RTL code using simulation tools

Verilog, System Verilog, Pcie, Cadence IES, Uvm, Power verification, Reset verification, Formal property checking tools, Contention checking, Synopsys VCS, Abstraction techniques, SVA, HBM, Gate level simulation