Process design rules, Analog layout design, Design verification tools, Layout methodologies, Voltage drop, Micro-floor planning, Ir, Floorplans, Signal planning, Esd, TSMC N3 technology, Electron migration, High speed SerDes layouts, Power grid

Pvs, Analog layout design, die-to-bump connectivity, package substrate interactions, R3D, PEX, analog layout matching techniques, EM, Ir, IC Layout design, LVS, CAD Tools, Floor Planning, Calibre, Xl, Esd, PowerFET, DRC, virtuoso, Packaging