Vdc, ADC, Charge pump, density, Antenna, noise fixes, Vlsi Design, custom analog layout design, Virtuoso XL, EDA Tools, RV high voltage flows, LDO, scripting skills, layout validation, Circuit Design, DRCs

Process design rules, Layout methodologies, Analog layout design, Electron migration, Voltage drop, High speed SerDes layouts, Micro-floor planning, IR ESD, TSMC N3 technology, Power grid, ESD bumps, Signal planning, Floorplans, Design verification tools

Automated PnR, High-speed SERDES IO PHY Layout design, Signal integrity issues, Analog IO design principles, CMOS and FinFET technologies, Block PnR