Uart, Nvme, Verilog, I2c, Pcie, Flash, system debug infrastructure, Uvm, system memory hierarchy, AMBA bus protocols, systemverilog, digital ASIC design and verification, formal verification, ARM cores and related infrastructure, CXL, DRAM, CPUSS C-based verification, multi-core SOC, SSP

simvision , Shell, Python, Perl, Cmake, UPF, JasperGold, Uvm, VC Formal, Siemens Questa, systemverilog, make, PropCheck, Verdi, Synopsys VCS, SVA, Zebu, CPF, DVE, Palladium, Cadence Xcelium, Veloce

Vcs, Perl, Python, Tcl, Debugging methodologies, Verdi, Assertions SVA, Xcelium, Uvm, ASIC SoC Verification Flows, systemverilog, Coverage-driven verification, spyglass, Simulation and regression flows, Jenkins Regression Automation Tools, DVE, Questa, Functional Verification