Shell scripting, Perl, DFT architecture and features, DFTMAX, ATPG pattern generation, Scan memory BIST, Verilog RTL design, JTAG 1149.x, IEEE1500, Scan Insertion, Test cost reduction analysis, ATPG patterns verification, Post silicon support, VCS simulation tool

Perl, Shell scripting, DFT verification, Synopsys Tetramax DFTMAX, VCS simulation tool, IEEE1500, Scan memory BIST, Verilog RTL design, JTAG 1149.x, Design for Test methodologies, Mentor testkompress

Shell scripting, DFT verification, Scan Insertion, Synopsys Tetramax DFTMAX, IEEE1500, memory BIST, Gate-level simulation, VCS simulation tool, JTAG 1149.x, Verilog RTL design, Scan, ATPG pattern generation, Mentor testkompress

Perl, Shell scripting, DFT verification, Synopsys Tetramax DFTMAX, VCS simulation tool, IEEE1500, Scan memory BIST, JTAG 1149.x, Verilog RTL design, Design for Test methodologies, Mentor testkompress