Shell scripting, Static Timing Analysis, Tcl, Verilog, System Verilog, Ethernet, Python, Pcie, Perl, Git, Dft, Synthesis, AXI-based interconnects, LINT, cdc, Sta, CXL, RDC

C, Vcs, Perl, Verilog, spyglass, cdc, Hardware Emulation Platforms, ASIC SoC development cycle, systemverilog, Rtl Design, EVE, Veloce, ASIC Design, formal verification

Digital RTL Design, VHDL, Timing Analysis, Logic Synthesis, Low-Power Design Techniques, systemverilog

Synthesis, ASIC Design, Rtl Design

Pcie, Version Control, Ethernet, RTL synthesis, Documentation, Timing Closure, verification processes, silicon bring-up, bare metal firmware development, SERDES, AI tools like Cursor

bist , Verilog, C, Vcs, Python, AHB, microcontroller platforms, Timing Analysis, systemverilog, digital timing constraints, DFT methodologies, Cadence Virtuoso, APB, Axi, ASIC tool flows, Questa, Timing Constraints, high-speed SerDes, ATPG, FPGAs, AMBA, XCelium, SOC interconnect fabrics, Genus Design Compiler, Asic verification, Scan Insertion, ASIC synthesis

code coverage , Verilog, System Verilog, LINT, cdc, AXI protocol, Low power synthesis, Formality, SoC level Synthesis, UPF, Rtl Design, Synthesis, AMBA, Timing Analysis, RTL Coding, AHB, ip development, functional coverage, front-end design tools

Uart, Spi, Verilog, I2c, LINT, cdc, MAS development, Sub-system design, SoC integration, ip design, Quality check flows, AMBA bus protocols, Axi, APB, RTL Coding, Medium complexity protocol, AHB, Microarchitecture

Rtl Design, Synthesis, ASIC development cycle, formal verification, ASIC design methodologies, architecture, Verification, Design Verification