Coverage, complex debug, CPU DV, RTL, high-performance out-of-order CPU verification, regressions, Uvm, testbench development, microarchitecture verification, AI-assisted verification workflows, Methodology, Isa, CVM, verification strategy

Tcl, Python, Perl, CI CD integration, assertion-based verification, CAD tool integration, coverage analysis, Uvm, regression automation, formal verification, systemverilog, dynamic verification

rtl development , Uart, Spi, Pcie, Perl, Verilog, I2c, Python, System Verilog, front-end design, Cadence Tools, gate-level simulations, Synthesis, Design Verification, DMA engines, micro-architecture development, Timing Closure, UVM-based design verification

Security Solutions, AI-ready Ethernet Fabrics, networking infrastructure, GSP Model, Data Center Switching, Campus Wi-Fi, Cloud Networking Observability, Network Security Automation

Ethernet Services, Embedded PCs, B2B Industrial Sales, Industrial Customers