Design for Testing (DFT), rtl development , System on a Chip (SoC) designs and integration, Verilog, Python, Perl, power analysis, LINT, processor design, cdc, arithmetic units, power closure, memory hierarchies, test plan and coverage analysis, FV, UPF checks, simulation debug, silicon bring-up, micro-architecture, bus architectures, Synthesis, ASIC SoC design verification, Timing, systemverilog, subsystem integration, accelerators, low-power design techniques

Unix, Usb, Linux, System Verilog, Jtag, Ethernet, Python, Perl, Pcie, TSN, UVM methodology, Design for Debug, ARM based SoC verification

Pcie, Systemc, Jenkins, Python, Perl, MATLAB, Design Verification, DV, Design Verification Lead, IP Verification, Subsystem Verification, systemverilog, Uvm, formal verification, Functional Verification, Constraint Random, Coverage Closure, Verification Plan, Specman E, Xcelium, Vmanager, Verilog-A, RNM, C Modelling, ISO 26262, Semiconductor, Pre-Silicon Verification

Usb, Ovm, Pcie, Ethernet, Test and coverage plan, Verification environment, Coverage, Assertion checkers, Uvm, VMM Test Harness, MIPI, Validation plan, System Verilog HVL, Scenario creation

Test Case Creation, Shell, Perl, Python, Advanced Debugging skills, Uvm, testbench development, coverage-driven verification, Computer Architecture concepts, Formal Verification techniques, Functional Verification, Rtl Design