C, Perl, Verilog, Shell scripting, Python, Tcl, SVA, UVM assertions, systemverilog

hardware engineering , System Verilog, Test Planning, testbench stimulus agent monitor checker development, Uvm, coverage driven constraint random verification, c based reference model, unit and IP level verification

Verilog, Uvm, testbench creation, code coverage analysis, DFI protocols, logic simulation, systemverilog, Verilog-A, score boarding, AMS simulations, RTL debugging

Uart, Nvme, Verilog, I2c, Pcie, Flash, system debug infrastructure, Uvm, system memory hierarchy, AMBA bus protocols, systemverilog, digital ASIC design and verification, formal verification, ARM cores and related infrastructure, CXL, DRAM, CPUSS C-based verification, multi-core SOC, SSP

System Verilog, Verilog, Uvm, Gate level verification, Ethernet IEEE 802.3, Display Port, Asic verification, MIPI protocols, Power aware verification