Scala, Python, System Verilog, Chisel, Uvm

C, DDR, Perl, System Verilog, Python, Tcl, AMBA protocols, Uvm, Axi, HBM, APB, LPDDR, AHB

scoreboard , test environments , Test Cases, C, Shell, Soc Architecture, Verilog, Agents, Mixed signal designs, Verification testbenches, Debugging RTL and Gate simulations, Verification methodology, Monitors, Regression systems, Testbenches, Sequencers, Industry-standard simulators, Revision control systems, Directed and constrained random verification methodology

System Verilog Testbench Architecture, Gate-Level Simulation and Debug, VERA System Verilog simulators

System Verilog, Verilog, Tcl, Python, Perl, Pcie, CXL

Spi, C, Uart, Verilog, Tcl, I2c, Bash, Python, Pcie, Perl, systemverilog, LPDDR, Uvm, i2s, DFX Verification, AHB, APB, Axi

Uart, Nvme, Verilog, I2c, Pcie, Flash, system debug infrastructure, Uvm, system memory hierarchy, AMBA bus protocols, systemverilog, digital ASIC design and verification, formal verification, ARM cores and related infrastructure, CXL, DRAM, CPUSS C-based verification, multi-core SOC, SSP

System Verilog, Verilog, Uvm, Gate level verification, Ethernet IEEE 802.3, Display Port, Asic verification, MIPI protocols, Power aware verification